1. Field of Invention
This invention relates to integrated circuit structures and fabrication thereof, and more particularly to an interconnect structure and a method of fabricating the same.
2. Description of Related Art
High-integration semiconductor IC chips generally have at least two layers of metal interconnect, which are called “multilevel interconnects” and are intended to fit the ever increased density of devices.
FIG. 1A depicts a cross section of an interconnect structure in the prior art. The structure 10a includes a substrate 100 with a copper line 102 therein, a metal barrier 104, a SiN barrier 106, a Si-based insulating layer 108 on the substrate 100 and a copper plug 110 in the layer 108. The SiN barrier 106 is disposed between the insulating layer 108 and substrate 100. The SiN barrier 106 and the layer 108 have therein an opening 109 exposing the copper line 102. The copper plug 110 is disposed in the opening 109 and electrically connected to the copper line 102. The metal barrier 104 is between the plug 110 and the sidewall of the opening 109 and between the plug 110 and the line 102.
With the development in the IC technology, the size of IC device is unceasingly reduced so that the width of the opening 109 is reduced accordingly. Thus, the current density in the copper plug 110 is raised so that the devices are easily damaged lowering the device reliability. Moreover, the metal barrier 104 usually includes tantalum (Ta), TaN or Ta/TaN having higher resistance than copper so that when the device size is reduced, the resistance ratio of the metal barrier 104 to the copper plug 110 is raised more causing an even higher resistance of the conductive structure 110+104.
Interconnect structures with carbon nanotubes instead of a copper plug have also been studied, in consideration that the sustainable current density of nanotubes is about 1000 times that of copper. FIG. 1B depicts such an interconnect structure 10b, which includes a substrate 100, a copper line 102 in the substrate 100, a metal barrier 104, an Si-based insulating layer 108 on the substrate 100, a Ta barrier 106, a cobalt or nickel layer 116 and a conductive plug 118 including carbon nanotubes. The metal barrier 104 is between the substrate 100 and copper line 102. The Ta barrier 106 is disposed between the insulating layer 108 and the substrate 100. The insulating layer 108 has therein an opening 109 exposing the Ta barrier 106. The cobalt or nickel layer 116 is disposed in the opening 109 on the Ta barrier 106. The conductive plug 118 including carbon nanotubes is disposed in the opening 109 on the cobalt or nickel layer 116.
However, when the Ta barrier 106 as a conductor is deposited on the whole die, as shown in FIG. 1B, the underlying copper line 102 is shorted with conductor structures in other areas via the Ta barrier 106. Since the Ta barrier 106 is difficult to pattern due to the high device density, such an interconnect structure 10b is difficult to apply.
For the interconnect structure 10b, researchers in Fujitsu Company and Infineon Technologies have made quite a few studies. In their methods, the catalytic layer 116 is formed on a conductive region of the substrate 100 by lithography and etching. A Si-based insulating layer 108 is formed, including SiO2 or SiO2 doped with other low-k material. An opening 109 is formed in the insulating layer 108 with lithography and etching. A CVD step is conducted with a carbon source gas so that carbon nanotubes as a plug 118 is formed in the opening 109 with the catalysis of the catalytic layer 116.
However, for the opening 109 is formed by lithography-etching, much process time is consumed. Moreover, since the carbon nanotubes have to be grown at a higher temperature in vacuum, the cost is higher. In summary, the fabricating process of the interconnect structure 10b is relatively complicated and the cost is relatively high.